Managing semiconductor memory array leakage current

US9792967B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Paul A. Bunce · Poughkeepsie, US
• Yuen H. Chan · Poughkeepsie, US
• John D. Davis · Gloucester, GB
• Silke Penth · Holzgerlingen, DE
• David Edward Schmitt · Rochester, US
• Tobias Werner · Holzgerlingen, DE
• Brian James Yavoich · Highland, US

Key dates

• Filing date: Jun 13, 2016
• Grant date: Oct 17, 2017
• Expiry date: Jun 13, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/419
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical “high” voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical “low” voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.