Volatile memory erasure by manipulating reference voltage of the memory
US9792977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2015 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Apr 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an erasure circuitry, a method for erasing a volatile memory, a volatile memory and erasure module in the form of computer readable instructions, where the erasure circuitry is adapted to erase the memory at occurrence of a predefined event. The erasure circuitry includes a negative pulse generator which is adapted to reduce the charge on capacitor in one or more volatile memory cells to zero logic by using a switch connected to the Voltage Reference (Vref) of the volatile memory cell, a controller and a negative power supply. The switch and the negative power supply impose a negative pulse on the Vref of the volatile memory cells on being instructed by the controller at the occurrence of a predefined event. An erasure module associated with the controller is provided for instructing the erasure circuitry for erasing data at the occurrence of a predefined event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.