Nonvolatile memories having data input/output switches for reducing parasitic capacitance of bus channel
US9793000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2015 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Jun 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory includes a memory cell array including a plurality of memory cells, a pad configured to be connected to a data input/output line, and an input/output circuit configured to receive data to be programmed in the memory cell array and to transmit data read from the memory cell array. The nonvolatile memory further includes a switch configured to couple and decouple the pad and the input/output circuit responsive to a switch control signal and a control circuit configured to generate the switch control signal responsive to a chip enable signal. Data storage devices and methods using such nonvolatile memories are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.