Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects

US9793163B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Robert L. Bristol · Portland, US
• Florian Gstrein · Portland, US
• Richard E. Schenker · Portland, US
• Paul A. Nyhus · Portland, US
• Charles H. Wallace · Portland, US
• Hui Jae Yoo · Hillsboro, US

Key dates

• Filing date: Sep 27, 2013
• Grant date: Oct 17, 2017
• Expiry date: Sep 27, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.