Power supply transient performance (power integrity) for a probe card assembly in an integrated circuit test environment
US9793226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Feb 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2896
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.