Insulating wall and method of manufacturing the same
US9793312B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Aug 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/812
Abstract
A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.