Multiple layer side-gate FET switch
US9793350B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2017 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Mar 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An exemplary FET includes a base and first and second stacked layer groups each having a nonconductive layer and a semiconductive layer adjacent the nonconductive layer. Source and drain electrodes are in low resistance contact with the semiconductive layers. First and second parallel trenches extend vertically between the source and drain electrodes to create access to first and second edges, respectively, of the layers. A 3-dimensional ridge is defined by the layers between the first and second trenches. A continuous conductive side gate extends generally perpendicular to the trenches and engages the first edges, the top of the ridge and the second edges. A gate electrode is disposed in low resistance contact with the conductive side gate. The figure of merit for the FET increases as the number of layer groups increases. A plurality of parallel spaced apart ridges, all engaged by the same side gate, can be utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.