Tunnelling field effect transistor
US9793351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2014 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Sep 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A tunneling field effect transistor, comprising a gate electrode layer, a gate dielectric layer, a source region, a connected region and a drain region, wherein the source region comprises a first source region and a second source region, the second source region comprising an inner layer source region and an outer layer source region. The connected region comprises an expansion region and a high-resistance region. The doping types of materials of the inner layer source and the outer layer source region are opposite, and the forbidden bandwidth of the material of the inner layer source region is less than that of the outer layer source region. The contact surface formed by way of covering the inner layer source region by the outer layer source region is a curved surface. Since a contact surface of an outer layer source region and an inner layer source region of a tunneling field effect transistor is of a curved surface structure, the contact area of the outer layer source region and the inner layer source region is increased, and the probability of tunneling of a carrier through the contact surface is increased. Therefore, the On-state current is increased, thereby having a good cu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.