Multiple layer quantum well FET with a side-gate
US9793353B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2017 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Mar 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2201/3215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An exemplary FET includes a substrate and multiple vertically stacked layer groups with each layer group having a quantum well semiconductive layer and a nonconductive layer adjacent the first quantum well semiconductive layer. Conductive source and drain electrodes in conductive contact with the semiconductive layers. A 3-dimensional ridge of the stacked layer groups is defined between spaced apart first and second trenches which are between the source and drain electrodes. A continuous conductive side gate is disposed on the sides and top of the ridge for inducing a field into the semiconductive layers. A gate electrode is disposed in conductive contact with the conductive side gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.