Apparatus and method of fabrication for GaN/Si transistors isolation
US9793389B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Jun 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/602
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method of fabricating a semiconductor device having an isolated first transistor circuit and an isolated second transistor circuit is provided. The method comprises providing a silicon on insulator (SOI) wafer and fabricating an isolated first silicon region and an isolated second silicon region on the SOI wafer wherein each of the first silicon region and the second silicon region is bounded on its sides by a trench filled with insulator material. The method further comprises fabricating an active area comprising GaN on each of the first silicon region and the second silicon region to form the first transistor circuit and the second transistor circuit and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.