Thin film transistor array panel
US9793409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Mar 31, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/13306
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises a multi-layered structure disposed over a substrate and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer disposed over the substrate and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the bottom sub-layer substantially defining a first indium to zinc content ratio; a middle sub-layer disposed over the bottom sub-layer and comprising a metal material; an upper sub-layer disposed over the middle sub-layer and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.