Range and process compensation for a digital phase locked loop (PLL) or frequency locked loop (FLL) circuit
US9793906B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Aug 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.