LDPC post-processor architecture and method for low error floor conditions
US9793923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2015 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Nov 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/116
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.