Standard format intermediate result
US9798519B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2015 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Sep 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/485
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor comprises an instruction pipeline, a shared memory, and first and second arithmetic processing units in the instruction pipeline, each capable of reading or receiving operands from and writing or providing results to the shared memory. The first arithmetic processing unit performs a first portion of a mathematical operation to produce an intermediate result vector that is not a complete, final result of the mathematical operation. The first arithmetic processing unit generates a plurality of non-architectural calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The second arithmetic processing unit performs a second portion of the mathematical operation, in accordance with the calculation control indicators, to produce a complete, final result of the mathematical operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.