Memory access for a vector processor
US9798550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2013 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Aug 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs) arranged into a plurality of CU groups. The memory is arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups. For each CU group a respective first memory address is determined and for each CU group, the data in the associated memory macro-block is accessed at the respective first memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.