Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction
US9799405B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2015 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Dec 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory controller includes a storage module configured to store data indicating threshold voltage shift read parameters and corresponding index values. The nonvolatile memory controller includes a status circuit configured to determine at least one usage characteristic of a nonvolatile memory device, and a read circuit configured to determine whether a usage characteristic meets a usage characteristic threshold. When a usage characteristic is determined to meet the usage characteristic threshold, the read circuit is configured to perform all subsequent reads of the nonvolatile memory device using a threshold voltage shift read instruction identified using one or more of the threshold voltage shift read parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.