Method of forming source/drain contact
US9799567B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2014 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Oct 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/8316
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.