3DIC based system with memory cells and transistors
US9799761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2016 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Nov 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 3D IC based system, the system including: a first layer including first memory cells including first transistors, where the first transistors include first transistor channels; a second layer overlying the first layer, the second layer including second memory cells including second transistors, where the second transistors include second transistor channels, where the second layer includes vertically oriented doped regions, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the first transistor channels and at least one of the second transistor channels are directly coupled to at least one of the vertically oriented doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.