Stitchable global clock for 3D chips
US9800232B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2016 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Mar 30, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing a stitchable clock mesh, a dual operation mode system, and a method for providing a master clock stratum are, in turn, provided for a 3D chip stack having two or more strata. The method for providing a stitchable clock mesh includes providing, by at least one clock mesh disposed on each stratum and having multiple sectors, a global clock signal to various chip locations. The method further includes collecting, by mesh data sensors on each stratum, mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The method also includes selectively performing, by joining circuitry, a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.