Clock and data recovery circuit and phase interpolator therefor
US9800234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2016 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Jul 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery circuit and a phase interpolator therefor are provided. The clock and data recovery circuit includes a phase-locked loop, a control unit and the phase interpolator, a receiving circuit, a serial-to-parallel conversion circuit. The phase interpolator is connected with the control unit of the clock and data recovery circuit, and the phase interpolator includes: an encoding circuit, two multiplexers, a clock mixer, and two differential to single-ended amplifiers. The control unit is configured to further control the encoding circuit to change a delay position for a clock outputted by the phase interpolator in a case that the data sampled in the current clock position is not the optimal sampled data, to lead or lag the clock, thereby forming a stable state in which the clock follows the data dynamically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.