Mapped FIFO buffering
US9800513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2015 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Mar 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network interface device for connection between a network and a data processing system, the network interface device comprising: a plurality of ports for receiving data packets directed to the data processing system. An interface services the ports in a predetermined order and writes the data packets to buffers of a common memory. Each buffer is part of one of a set of linked logical sequence of buffers forming virtual queues in the common memory. Each virtual queue is associated with a port. A memory manager selects buffers of the common memory so as to cause the interface to populate the plurality of virtual queues with data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.