Scheme to measure individually rise and fall delays of non-inverting logic cells
US9804225B2 · kind B2 · utility
1Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2014 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jan 2, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.