Method of manufacturing array substrate and array substrate
US9804466B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 13, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jun 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/043
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of manufacturing an array substrate includes: forming a first functional layer comprising a plurality of array substrate areas and connection areas between adjacent array substrate areas; forming a plurality of conductive portions within each of the array substrate areas, the plurality of conductive portions extending from a corresponding one of the array substrate areas to a corresponding one of the connection areas and terminals of the plurality of conductive portions being in connection with capacitor lines within the corresponding one of the connection areas such that two capacitor lines between two adjacent array substrate areas face each other and are formed into a first capacitor element; forming a plurality of second functional layers on the first functional layer formed with the plurality of conductive portions and the capacitor lines, for forming a plurality of array substrates; and performing a cutting process at the connection areas between adjacent array substrates and removing the capacitor lines between the adjacent array substrates so as to form a plurality of separate array substrates. The present disclosure further provides an array substrate manufactured…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.