Method and apparatus for efficiently managing architectural register state of a processor
US9804842B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2014 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Sep 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: a source mask register to be logically subdivided into at least a first portion to store a usable portion of a mask value and a second portion to store an indication of whether the usable portion of the mask value has been updated; a control register to store an unusable portion of the mask value; architectural state management logic to read the indication to determine whether the mask value has been updated prior to performing a store operation, wherein if the mask value has been updated, then the architectural state management logic is to read the usable portion of the mask value from the first portion of the source mask register and zero out bits of the unusable portion of the mask value to generate a final mask value to be saved to memory, and wherein if the mask value has not been updated, then the architectural state management logic is to concatenate the usable portion of the mask value with the unusable portion of the mask value read from the control register to generate a final mask value to be saved to memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.