Concurrent validation of hardware units
US9804911B2 · kind B2 · utility
2Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2015 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jun 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes holding a definition of multiple software-implemented tests for testing one or more hardware units of an Integrated Circuit (IC), and of invocation conditions that specify whether the tests are permitted to run. The tests are applied to the hardware units at least partially in parallel, using a processor in the IC, by repeatedly tracking respective execution states of the tests and evaluating the invocation conditions, and invoking a test that currently does not run but is permitted to run in accordance with the invocation conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.