Prefetching weights for use in a neural network processor
US9805304B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Dec 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for performing neural network computations for a neural network, the circuit comprising: a systolic array comprising a plurality of cells; a weight fetcher unit configured to, for each of the plurality of neural network layers: send, for the neural network layer, a plurality of weight inputs to cells along a first dimension of the systolic array; and a plurality of weight sequencer units, each weight sequencer unit coupled to a distinct cell along the first dimension of the systolic array, the plurality of weight sequencer units configured to, for each of the plurality of neural network layers: shift, for the neural network layer, the plurality of weight inputs to cells along the second dimension of the systolic array over a plurality of clock cycles and where each cell is configured to compute a product of an activation input and a respective weight input using multiplication circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.