Dual-range clock duty cycle corrector
US9805773B1 · kind B1 · utility
19Cited by
1References
22Claims
0Family size
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Key dates
| Filing date | May 23, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | May 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.