Memory device, memory module, and memory system
US9805802B2 · kind B2 · utility
6Cited by
23References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Sep 14, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.