Semiconductor memory devices, memory systems including the same and methods of operating the same
US9805827B2 · kind B2 · utility
6Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2015 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Aug 4, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.