Semiconductor memory device
US9806028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2015 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jul 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a device isolation in a trench that defines first to third active patterns that are spaced apart from each other and having a long axis parallel to a first direction, first and second word lines extending in a second direction perpendicular to the first direction, a bit line, and a source line. The first and second active patterns are arranged in the second direction to constitute a column. The third active pattern is at a side of the column. The first word line intersects the first and second active patterns. The second word line intersects the third active pattern. When viewed from a plan view, the bit line extends in the first direction between the first and third active patterns, and the source line extends in the first direction between the second and third active patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.