Semiconductor wafer, semiconductor structure and method of manufacturing the semiconductor wafer
US9806036B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Nov 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54493
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first bevel region formed along the outer periphery of the main body, including a first slope connecting the first and second surfaces and having a first height with respect to a straight line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet, and a second bevel region in contact with the recess or opening, including a second slope connecting the first and second surfaces and having a second height, different from the first height, with respect to a straight line extending from a third point where the first surface and the second slope meet to a fourth point where the second surface and the second slope meet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.