Chip package having die structures of different heights and method of forming same
US9806058B2 · kind B2 · utility
53Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jan 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/182
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.