Analog/digital converter with charge rebalanced integrator
US9806552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jun 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02J7/345
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.