Low drop out compensation technique for reduced dynamic errors in digital-to-time converters
US9806759B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jul 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/361
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An apparatus comprises a radio frequency (RF) transceiver circuit; a phase modulator that comprises digital-to-time converter (DTC) circuitry configured to convert a digital value to a specified signal phase of a signal transmitted by the RF transceiver circuit; low drop out regulator (LDO) circuitry operatively coupled to the DTC circuitry, wherein a bias current of the LDO circuitry is adjustable; and logic circuitry operatively coupled to the LDO circuitry and DTC circuitry, wherein the logic circuitry is configured to set the adjustable bias current of the LDO circuitry according to a digital value input to the DTC circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.