Method and apparatus to minimise the onset and recovery time of a silicon photomultiplier
US9810795B2 · kind B2 · utility
6Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2008 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | May 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F77/959
- WIPO fieldEnvironmental technology
- WIPO sectorChemistry
Abstract
Silicon photomultiplier circuitry is provided that comprises at least one silicon photomultiplier pixel, each pixel comprising a plurality of silicon photomultiplier microcells. The silicon photomultiplier circuitry comprises control circuitry adapted to maintain a substantially constant voltage on a connection node between microcells of the pixel. The control circuitry is adapted to minimize the onset and recovery time of an output signal by maintaining a substantially constant voltage on the connection node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.