System and method for synchronization among multiple PLL-based clock signals
US9811113B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Jul 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.