Buffer memory devices, memory modules and solid state disks with non-uniform memory device connections
US9811265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Jul 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes at least two rows of memory device packages on a substrate and coupled to a control signal line. A first memory device package in a first row is connected to the control signal line at a first point closest to the proximal end of the control signal line and a second memory device in a second row is connected to the control signal line at a second point next closest to the first point. A signal trace length between the first memory device and the second memory device may be greater than a signal trace length between the first memory device package and a third memory device package immediately adjacent the first memory device package in the first row or a signal trace length between the second memory device package and a fourth memory device package immediately adjacent the second memory device package in the second row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.