Data buffer for multiple DIMM topology
US9811266B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 22, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Sep 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the embodiments include systems and devices that include a memory controller circuit element, and a printed circuit board (PCB). The PCB can include a memory module element; and a data buffer circuit element, the data buffer circuit element electrically connected to the memory controller circuit element and configured to receive instructions and data from the memory controller circuit element, the data buffer circuit element electrically connected to the memory module circuit element directly or through a socket, the data buffer circuit element configured to transmit instructions and data originated from the memory controller circuit element to the memory module circuit element and transmit data back to the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.