Arbitration signaling within a multimedia high definition link (MHL 3) device
US9811495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2014 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Jan 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for interfacing with a multimedia communication link comprises a half-duplex translation layer circuit operating in half-duplex and a full-duplex link layer circuit to communicate over a control bus of the multimedia communication link in full duplex. The apparatus further comprises an arbitration circuit communicatively coupled between the half-duplex translation layer circuit and the full-duplex link layer circuit, the arbitration circuit to control data flow between the half-duplex translation layer circuit and the full-duplex link layer circuit. The arbitration circuit provides interface and signaling rules for transmitting packets from the half-duplex translation layer circuit to the full-duplex link layer circuit, receiving packets via the full-duplex link layer circuit at the half-duplex translation layer circuit, and resolving conflict arising due to bidirectional data flow at the arbitration logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.