Low latency device interconnect using remote memory access with segmented queues
US9811500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2014 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Dec 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/104
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A writing application on a computing device can reference a tail pointer to write messages to message buffers that a peer-to-peer data link replicates in memory of another computing device. The message buffers are divided into at least two queue segments, where each segment has several buffers. Messages are read from the buffers by a reading application on one of the computing devices using an advancing head pointer by reading a message from a next message buffer when determining that the next message buffer has been newly written. The tail pointer is advanced from one message buffer to another within a same queue segment after writing messages. The tail pointer is advanced from a message buffer of a current queue segment to a message buffer of a next queue segment when determining that the head pointer does not indicate any of the buffers of the next queue segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.