Reducing latency in an expanded memory system
US9812186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2015 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Apr 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delay processing on a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem and reduces the memory access time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.