Read and write apparatus and method for a dual port memory
US9812189B2 · kind B2 · utility
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15References
19Claims
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Key dates
| Filing date | Jun 4, 2015 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Jun 4, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.