Buffered multi-rank memory modules configured to selectively link rank control signals and methods of operating the same
US9812220B2 · kind B2 · utility
9Cited by
2References
10Claims
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Key dates
| Filing date | Jul 12, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Jul 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.