Nanoscale patterning method and integrated device for electronic apparatus manufactured therefrom
US9812333B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 26, 2014 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Apr 18, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a nanoscale patterning method using self-assembly, wherein nanoscale patterns having desirable shapes such as a lamella shape, a cylinder shape, and the like, may be formed by using a self-assembly property of a block copolymer, and low segment interaction caused in a structure of 10 nm or less which is a disadvantage of the block copolymer may be prevented. In addition, even though single photolithography is used, pattern density may double as that of the existing nano patterns, and pitch and cycle of the patterns may be controlled to thereby be largely utilized for electronic apparatuses requiring high integration of circuits such as a semiconductor device, and the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.