Prevention of premature breakdown of interline porous dielectrics in an integrated circuit
US9812399B2 · kind B2 · utility
1Cited by
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14Claims
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Assignee
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Key dates
| Filing date | Apr 25, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Apr 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0217
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.