Circuit structure for enhancing EFT immunity of primary side converter
US9812945B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2015 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Nov 10, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a circuit structure for enhancing EFT immunity of primary side converter, including a power ground and a feedback voltage detecting block, a feedback current detecting block, a controller, a PWM driving block, a high voltage starting block, a starting unit, a circuit for enhancing EFT immunity of primary side converter, a power MOS transistor, and an OR gate configured to perform a logical OR of an off-time calculated theoretically and an off-time output by an off-time control block. The present disclosure enhances EFT immunity effectively and improves the dynamic characteristics of the primary side converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.