Active gate clamping for inverter switching devices using grounded gate terminals
US9813009B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2017 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Feb 7, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02T10/72
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An inverter for an electric vehicle comprises a phase leg having series-connected upper and lower transistors between a positive bus and a ground bus. Upper and lower gate drive circuits supply gate drive signals to the upper and lower transistors. Each gate drive circuit includes an active clamp for deactivating the upper and lower transistors. The transistors are comprised of semiconductor devices, each having respective gate, collector, and emitter terminals. Each pair of gate and emitter terminals is adapted to provide an enhanced common source inductance therebetween. Each gate terminal is adapted to be tied to a ground voltage of the drive circuits. Each respective active clamp is comprised of a p-channel MOSFET having a source terminal connected to the gate terminal of a respective transistor and having a drain terminal connected to the emitter terminal of the respective transistor bypassing the respective enhanced common source inductance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.