Embedded buffer circuit compensation scheme for integrated circuits
US9813046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Mar 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10378
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatus and methods using a package substrate and a die coupled to the package substrate. The package substrate includes conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate. The die includes buffer circuits and a calibration module coupled to the buffer circuits and the resistor. The buffer circuits include output nodes coupled to the conductive contacts through the conductive paths. The calibration module is configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.