Integrated coherent receiver having a geometric arrangement for improved device efficiency
US9813163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | May 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/4286
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed herein is a monolithically integrated coherent receiver chip which has a geometric arrangement of the on-chip components that significantly improves the performance and the manufacturability of a coherent receiver module for Dual Polarization Quadrature Phase Shift Keyed (DP-QPSK) applications and other optical coherent detection systems. The coherent receiver chip comprises two optical hybrids, three optical inputs and eight electrical outputs with the two optical hybrids oriented perpendicular to the optical inputs and the electrical outputs which are widely spaced and arranged in a co-linear fashion that simplifies module design and assembly. The proposed geometric arrangement also replaces any optical waveguide crossings with vertical electrical-optical crossings and includes electrical transmissions which are used to minimize channel skew. The proposed configuration also has the additional benefit of improved thermal management by separating the module's trans-impedance amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.