Method for detecting timing references affected by a change in path delay asymmetry between nodes in a communication network
US9813175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2013 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Oct 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for detecting a timing reference affected by a change in path delay asymmetry in a communications network comprising a master node having a master clock and a plurality of slave nodes each having a respective slave clock is provided. The method comprises: determining that a first timing reference received by a first slave node indicates a time correction to its slave clock greater than a time correction threshold; determining whether one or more other slave nodes have received a timing reference indicating a time correction to their slave clock greater than a time correction threshold; and determining whether the first timing reference is affected by a change in path delay asymmetry based on the determining of whether one or more other slave nodes have received a timing reference indicating a time correction to their slave clock greater than a time correction threshold. Apparatus and a computer program for detecting a timing reference affected by a change in path delay asymmetry in a communications network are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.